Jeanine Cook, PhD
Associate Professor, Klipsch School of Electrical and Computer Engineering
New Mexico State University, Las Cruces, NM 88003
Office: Thomas and Brown 127
I currently direct the Advanced Computer Architecture Performance and Simulation Laboratory. I teach courses in computer architecture and have research interests in the areas of microarchitecture simulation techniques, performance modeling and analysis, workload characterization, and microarchitectural power optimizations. When I'm not working, I'm out in the desert or wilderness riding my horse, Ringo Starr, or I'm hanging out with my dogs, chickens, and cats. I'm married to a wonderful guy who also enjoys the outdoors on his mule, Max.
Advanced Computer Architecture Performance and Simulation Laboratory (ACAPS)
Army High Performance Computing Research Center
R. Srinivasan, E. Frachtenberg, S. Pakin, O. Lubeck, J. Cook. "An Idealistic Neuro-PPM Branch Predictor". The Journal of Instruction Level Parallelism, vol. 9, May 2007.
S. Talli, R. Srinivasan, J. Cook. " Compiler-Directed Functional Unit Shutdown for Microarchitecture Power Optimization". Proceedings of the 26th IEEE International Performance Computing and Communications Conference (IPCCC), New Orleans, LA. Apr 2007.
R Srinivasan, E.Frachtenberg, S.Pakin, O.Lubeck, J.Cook. "Neuro-PPM Branch Prediction". Proceedings of the 2nd JILP Championship Branch Prediction Competition (CBP-2) held in conjunction with MICRO- 39. Orlando, FL. Dec 2006.
R. Srinivasan, J. Cook, O. Lubeck. "Ultra-Fast CPU Performance Prediction: Extending the Monte Carlo Approach". Proceedings of the IEEE International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Brazil. Oct 2006.
R. Srinivasan, J. Cook, O. Lubeck. " Performance Modeling Using Monte Carlo Simulation". IEEE Computer Architecture Letters, Volume 5, Apr. 2006.
W. Mathur, J. Cook. "Improved Estimation for Software Multiplexing of Performance Counters". Proceedings of the IEEE International Symposium on Modeling, Analysis, Simulation of Computer and Telecommunication Systems, Atlanta, GA. Sep 2005.
R. Srinivasan, J. Cook, S. Stochaj. "Exploiting benchmark patterns for Efficient Microarchitecture Simulation". Proceedings of the International Computer Systems and Information Technology Conference, Algiers, Algeria. Jul 2005.
R. Srinivasan, J. Cook and S. Cooper. "Fast, Accurate Microarchitecture Simulation Using Statistical Phase Detection". Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, Austin, TX. Mar 2005.
P. Bandini, J. Cook, M. Mitchell, L. Riley. "A New Paradigm for Optimizing Hybrid Simulations of Rare Event Modeling for Complex Systems". Proceedings of SCS Advanced Simulation Technologies Conference. Arlington, VA. Apr 2004.
R. Srinivasan and J. Cook. “Fast, Accurate Micro-architecture Simulation". Proceedings of the ITEA Modeling and Simulation Workshop. Las Cruces, NM. Dec 2003.
W. Mathur, J. Cook. "Towards
Accurate Performance Evaluation using Hardware Counters". Proceedings of
the ITEA Modeling and Simulation Workshop. Las Cruces, NM. Dec
S. Ramanathan, R. Srinivasan and J. Cook. “Intrinsic Data Locality of Modern Scientific Workloads". Proceedings of the IEEE 6th International Workshop on Workload Characterization, Austin, TX. Oct 2003.
J. Cook, R. Oliver and E. Johnson. "Toward Reducing Processor Simulation Time via Dynamic Reduction of Microarchitecture Complexity". Proceedings of ACM SIGMETRICS Performance Evaluation Review. Marina Del Rey, CA. Jun 2002.
J. Cook, R. Oliver and E. Johnson. "Examining
Performance Difference in Workload Execution Phases". Proceedings of
IEEE 4th Annual Workshop on Workload Characterization. Austin, TX. Dec
"A Monte Carlo Approach to Modeling Processor Performance". Ramkumar Srinivasan. 2007
Master Thesis, Technical reports
"An Analytic Regression Model for Performance Prediction of the Opteron Processor". Kiran Mothekani. 2007
"Validating Processor Power Models through Real-Time Temperature Measurement". Nishchay Bharati. 2007
"Compiler-Directed Functional Unit Shut-Down for Microarchitecture Power Optimization". Santosh Talli. 2006
"Increasing Computational Utilization Through Grid Computing". Rajesh Nayar. 2006
"A Self-contained Power-aware FPGA Based Data Acquisition Architecture for Satellite Systems". Subhash Gutti. 2006
"Increasing Simulator Speed by Optimizing the Mapping Between the Native Architecture and the Simulator: A Look at Simulator Workload Characterization". Lee Finley. 2005
"Uniprocessor Performance Analysis of Representative Workload Of Sandia Laboratories' Scientific Applications". Charles Laverty. 2005
"Understanding the Effects of Microarchitectural Parameters on the Uniprocessor Performance of Sandia Scientific Applications". Dana Hardin. 2005
"Modeling the Effects of Speculative Instruction Execution in a Functional Cache Simulator ". Amol Pandit. 2005
"Techniques for Accelerating Microprocessor Simulation". Ram Srinivasan. 2004
"Static and Dynamic Workload Characterization of SPEC SPU2000 Workloads". Kunxiang Yan. 2004
"Toward Accurate Performance Evaluation Using Hardware Counters". Wiplove Mathur. 2004
"An FPGA Implementation of a MIPS RISC Processor for Computer Architecture Education". Victor Rubio. 2004
"IntrinsicData Locality of Modern Scientific Workloads". Sharath Ramanathan. 2003
"Dynamic Detection of Workload Execution Phases". Matthew Alsleben. 2002
Updated on April 10, 2008