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Hello! I'm a PhD student at New Mexico State University. My research interests include micro-architecture design and performance modeling. I am advised by Prof. Jeanine Cook.  

Statistical performance models

This project aims to build statistical models to predict performance of modern processors. A Monte Carlo model to predict CPI for the Itanium and Niagara architecture has been developed. Model extensions to support SMP/CMP is currently under development.

Power-Aware compiler optimization

This research proposes to develop compiler optimization techniques that minimize software induced processor power consumption. Presently our focus is on reducing cache and functional-unit leakage power.

Identifying statistically valid simulation points

The execution of a workload is marked by regions of repeating behavior (phase). This research provides a framework for identifying regions of unique behavior. Simulating only the unique regions, cuts down the simulation time for SPEC2000 from 5 months to 5 days.
 

Parallel micro-architecture simulation

SimpleScalar is one of the most widely used micro-architecture simulators in academia. One of main drawbacks of SimpleScalar is its poor simulation speed. In this research project, a method to effectively parallelize the execution of the SimpleScalar simulator was developed.
 

Ram Srinivasan, Olaf Lubeck and Jeanine Cook. "A Microarchitecture Performance Model for the Cell Broadband Engine". Under review.

Ram Srinivasan, Eitan Frachtenberg, Scott Pakin, Olaf Lubeck and Jeanine Cook. "An Idealistic Neuro-PPM Branch Predictor". The Journal of Instruction Level Parallelism, Volume 9, May 2007.

 

Santosh Talli, Ram Srinivasan and Jeanine Cook. "Compiler-Directed Functional Unit Shutdown for Microarchitecture Power Optimization". Proceedings of the 26th IEEE International Performance Computing and Communications Conference (IPCCC), New Orleans, LA. Apr 2007.

 

Ram Srinivasan, Eitan Frachtenberg, Scott Pakin, Olaf Lubeck and Jeanine Cook. "Neuro-PPM Branch Prediction". Proceedings of the 2nd JILP Championship Branch Prediction Competition (CBP-2) held in conjunction with MICRO-39. Orlando, FL. Dec 2006.

 

Ram Srinivasan, Jeanine Cook and Olaf Lubeck. "Ultra-Fast CPU Performance Prediction: Extending the Monte Carlo Approach". Proceedings of the IEEE International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Brazil. Oct 2006.

 

Ram Srinivasan, Jeanine Cook and Olaf Lubeck. "Performance Modeling Using Monte Carlo Simulation". IEEE Computer Architecture Letters. Volume 5, Number 1, 2006.

 

Ram Srinivasan and Olaf Lubeck. "MonteSim: A Monte Carlo Performance Model for In-order Microarchitectures". Workshop on Binary Instrumentation and Applications (WBIA-05), held in conjunction with PACT 2005. St Louis, MO. Sep 2005. ACM Computer Architecture News Special Issue. Volume 33, Issue 5. Dec 2005.

 

Ram Srinivasan, Jeanine Cook and Steve Stochaj. "Exploiting Benchmark Patterns for Efficient Microarchitecture Simulation". Proceedings of the International Computer Systems and Information Technology (ICSIT) Conference, Algeria. Jul 2005.

 

Ram Srinivasan, Jeanine Cook and Shaun Cooper. "Fast, Accurate Microarchitecture Simulation Using Statistical Phase Detection". Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Austin, TX. Mar 2005.

 

Ramkumar Srinivasan and Jeanine Cook. “Fast, Accurate Micro-architecture simulation". Proceedings of the ITEA Modeling and Simulation Workshop. Las Cruces, NM. Dec 2003.

Sharath Ramanathan, Ramkumar Srinivasan and Jeanine Cook. “Intrinsic Data Locality of Modern Scientific Workloads". Proceedings of the IEEE 6th International Workshop on Workload Characterization (WWC), Austin, TX. Oct 2003.

 

 

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